The present invention relates to a multi-layer wiring substrate, which has a build-up laminated body configured by repeatedly laminating insulating layers and wiring layers alternately on a carrier substrate, and a method for manufacturing the substrate, and, in particular, to a multi-layer wiring substrate, which has a feature in the configuration of a carrier substrate for realizing higher density, and a method for manufacturing the substrate.
Miniaturization of electronic equipments is rapidly promoted, and a technical outlook has been presented, in which the thin film technology is made use of to realize 0.25 mm pitch with respect to packaging of semiconductors, as described in xe2x80x9cNikkei Micro Devicexe2x80x9d (August 1998, pp. 66 to 71).
A wiring substrate to be incorporated into such package includes a known multi-layer wiring substrate having a build-up laminated body. Such multi-layer wiring substrate having a build-up laminated body is herein referred to as a build-up substrate.
In basic technology for build-up substrates is, as disclosed in, for example, Japanese Patent No. 2739726 (Japanese Patent Unexamined Publication No.4-148590), high density packaging is realized by using the fine processing technique of a build-up layer, in which insulating layers and wiring layers are stacked one by one alternately on front and back surfaces of a printed wiring board.
However, at the stage when such technique presented itself, a core wiring substrate (to be a carrier substrate) and front and rear build-up layers are connected by forming holes by means of drilling and applying plating to such holes, which gives rise to such problems that density of the entire substrate is limited by accuracy of the drilling, and the holes restricts a wiring area.
Among those problems, restriction on the wiring area is solved by the development of that technique, in which through holes are formed in a printed substrate (that is, a carrier substrate and also called a core substrate) being a core, the through holes are filled with a resin, and then the build-up technique is applied. A structure of a semiconductor device, in which a semiconductor chip (LSI) is mounted on a multi-layer wiring substrate obtained by the build-up technique, is shown in FIG. 1.
As shown in FIG. 1, a pitch xe2x80x9cbxe2x80x9d of through holes 12 in a core substrate 10, formed by drilling is normally larger than a pitch xe2x80x9caxe2x80x9d of terminals (solder connection) 2 on an LSI indicated by the reference numeral 1. Therefore, when wiring layers 16 on the core substrate 10 are to be connected to wiring layers 13 on a build-up layer 11, wiring from the LSI terminals 2 to the through holes 12 in the core substrate 10 is necessarily formed by using wiring layers 13 in the build-up layer 11, in which insulation layers 15 and the wiring layers 13 are stacked alternately, build-up layer vias 14, and lands 16a about opening portions of the through holes 12, and thus direct connection between the LSI terminals 2 and the through holes 12 has in no way been taken into consideration.
The problem of restriction on density due to drilling has been successfully solved by the advent of the so-called coreless technique, in which the use of a printed board for a core is abandoned, and wiring sheets having fine front-to-back conductive passages formed with the laser processing and the like are stacked one another.
However, in addition to the problem such as handling required for suppressing deformation of sheets, such coreless structure offers a problem in losing an advantage of the conventional build-up technique capable of advancing most processing steps simultaneously on front and back parts.
Accordingly, an object of the present invention is to solve the problems of the abovedescribed conventional build-up substrate, and to provide a multi-layer wiring substrate, which realizes a carrier substrate enabled to be formed with through holes in high density, and applies the conventional build-up technique to the carrier substrate to form build-up layers thereon for high density packaging, and a manufacturing method thereof.
Therefore, to attain the above-described purposes, the inventors of the present application have investigated the functions of through holes on a core substrate in a conventional build-up substrate shown in FIG. 1. As a result, one of the functions is the provision of electric connection in a power source, grounding, signals and so on, etc. between build-up layers 11, which are formed on front and back sides of the core substrate . Another function is the provision of connection to signal layers in the core substrate 10 although limited to the case where multi-layer substrates are used.
Since the core substrate 10 is normally low in wiring density as compared with that in the build-up layers 11, only the connecting function in connection with the front and back sides of the core substrate is necessary provided that the core substrate 10 be not provided with any wiring function. Hereupon, a carrier substrate will be demanded, in which through holes are arranged in high density with a desired dimensional accuracy.
FIG. 2 shows a structural model of an ideal build-up substrate 20 having a terminal pitch xe2x80x9caxe2x80x9d for a LSI, and so a pitch xe2x80x9cbxe2x80x9d of conductors 17 connecting front and back sides of the core substrate 20 to each other must be naturally made fine to a level of the terminal pitch xe2x80x9caxe2x80x9d of the LSI (the pitch a=b). It is estimated that such pitch will be made fine to 0.25 mm around the year 2002 to 2003, and if this is not realized, rewiring from an LSI to a core conductor will be needed as in the prior art. The reference signs 1, 2, 11, 13, 13a, and 15 refer to the same elements shown in FIG. 1, and therefore need not describe herein.
However, it is not necessary for through holes to be arranged in the same pitch on the level of the carrier substrate, and the pitch of the through holes can be preferably converted to the pitch of the build-up layer or of terminals of the semiconductor package, so it sufficing that the through holes per unit area can be secured in quantity as required. In view of the above, the present invention proposes a structure, which premises that a plurality of through holes are simultaneously formed in a small area.
The inventors of the present application have performed various experiments on the basis of the above investigation result to obtain an important knowledge that can attain the object of the invention as described below in details.
More specifically, a plurality of windows are provided in a foil of copper, a measure such as the blacking treatment, Ni plating and the like is used to form an irregular surface on the copper surface, and an insulating resin layer is formed closely on the surface, so that the windows are filled with the resin. The insulating resin includes resins, such as a solder resist of epoxy resin group or polyimide, which are conventionally used as an interlayer insulating film for a multi-layer wiring structure.
With such construction, it is possible to set a coefficient of thermal expansion of the entire structure close to that of the copper foil, and so to reduce a load in the thermal process. of course, a metal foil other than copper may be used in order to obtain a line expansion coefficient other than that of copper in applications of semiconductor packages and so on. This kind of resin-coated copper foil with windows is disclosed in, for example, Japanese Patent Unexamined Publication No. 6-268381, which provides a process for laminating the copper foil but does not suggest lines, in which the copper foil is used for a carrier substrate in the build-up technique.
Then, the inventors of the present application have investigated a measure of forming a plurality of through holes in window portions of the copper-resin complex structure, which has a handling quality. While the carbon dioxide laser offers a large processing speed up to 50,000 nm, the high-frequency YAG laser having an ultraviolet wavelength may be more useful in a smaller range, but is disadvantageous in a small processing speed.
Such small processing speed is attributed to a limitation of a resin in ultraviolet transmittance, and is hard to dramatically increase in output. Hereupon, the processing speed can be increased by reforming a laser beam into a multi-beam by optical means, and simultaneously forming a plurality of holes.
In configuring such an optical system for reforming into a multi-beam, the processing in a narrow region is necessarily required. The present invention realizes the processing by concentrating the hole formation processing at the window portions of a copper foil. After the formation of holes, a plurality of through holes at the window portions can be formed by applying a catalyst and performing copper plating after the desmire treatment of resin (one for removing processed residues) or the coarsening treatment is carried out. A pitch of these plurality of through holes should not be determined by the technology related to the hole processing but should be determined by the inter-layer registering technology.
In addition, a similar function can be achieved by the following measures. Such measures is the same as described above with respect to the procedure, by which the resin coated copper foil with windows (open window sheet) is formed, but subsequently a second window having a particular shape is formed in the window filled with the resin.
More specifically, the second window is formed to have a plurality of irregular portions, which are disposed radially, and comprise mountains and valleys extending adjacent to each other on wall surfaces in the insulating resin layer region, which is disposed in the window filled with the resin, to be spaced a substantially equal distance from the center point of the window. Such technique includes punch working with the use of, for example, molds. Portions to processed are disposed only within a region of a resin layer, which is filled in the window, and are enabled enough to be subjected to punch working, and a contrivance in the process, in which the whole portions are heated, can be applied to provide an increase in throughput. However, if the window is made fine, laser beam processing is desirable.
Subsequently, the coarsening treatment is performed on the surface, and application of a catalyst and copper plating is effected to cover the entire surface with copper. Thereafter, a plurality of copper lines along the internal wall of the punched hole can be obtained by using drilling to remove only the central portion of the second window.
Thereafter, the interior of the second window is again filled with a resin in a similar method and the copper portions on the front and back surfaces are subjected to etching process into a desired shape to enable forming a plurality of conductive paths for one copper foil window. If filling in the holes in the subsequent process is unnecessary, such filling is not needed provided that a liquid resist is used for separating the patterns on the front and back surfaces. The resist is preferably of a positive type.
While drilling is used in this example to remove a portion (convex portion) of the copper plating formed inside the second window, a desired structure can be obtained as by removing the catalyst at the unnecessary portions in a similar manner after the application of the catalyst. In a simplest way, it is suitable to shave off the resin in the convex portions by means of drilling after the application of the catalyst or to polish the surface thereof so as to remove the catalyst in the portions.
Also, a resin-coated copper foil with a window (a copper foil having a window filled with the resin) may be a laminated structure, and it is apparent that the use of two sheets of copper foils with a material of high dielectric constant interposed therebetween can easily form a capacitor. In this case, if a region where the conductive paths (through holes) connecting the front and back surfaces are formed is separated from the copper foil in a planar manner, the total area required for making the through holes clear of the power source can be made small to contribute to enhancement of the capacity of the capacitor.
The multi-layer wiring substrate of the invention is formed with a wiring structure, which is composed of a build-up laminated body formed by repeatedly stacking insulation layers and wiring layers on a carrier substrate . The carrier substrate comprises a copper foil provided with a plurality of windows in regular configuration; an insulating resin layer, which is filled in the windows of the copper foil and coats the copper foil; and a plurality of independent conductive paths, which are provided in regions of the insulating resin layer filled in the windows of the copper foil, and extend from a front side of the substrate to a back side thereof.
Desirably, the plurality of independent conductive paths, which are provided in regions of the insulating resin layer filled in the windows of the copper foil, and extend from a front side of the substrate to a back side thereof, are provided radially to be spaced a substantially equal distance from centers of the respective second windows.
Preferably, the copper foil, which is provided with a plurality of windows in regular configuration and constitutes the carrier substrate, comprises a laminated body, in which plural layers of copper foil stick to one another with insulating materials interposed there-between, and the laminated body, in which plural layers of copper foil stick to one another with insulating materials interposed therebetween, comprises a laminated body, in which an insulating material mixed with a high dielectric filler as the insulating materials and having a dielectric constant of 10 or more as a whole is used to stick the plural layers of copper foil.
A method of manufacturing a multi-layer wiring substrate including a wiring structure, which is composed of a build-up laminated body formed by repeatedly stacking insulation layers and wiring layers on a carrier substrate . The carrier substrate is formed by the steps of forming a plurality of windows in a copper foil in regular configuration; forming an insulating resin layer, which is filled in the windows of the copper foil and coats the copper foil with a uniform thickness; and forming a plurality of independent conductive paths, which are provided in regions of the insulating resin layer filled in the windows of the copper foil, and extend from a front side of the substrate to a back side thereof.
In one aspect of the invention, the plurality of independent conductive paths, which are provided in regions of the insulating resin layer filled in the windows of the copper foil, and extend from a front side of the substrate to a back side thereof, are provided radially to be spaced a substantially equal distance from centers of the respective second windows.
Preferably, the copper foil, which is provided with a plurality of windows in regular configuration and constitutes the carrier substrate, comprises a laminated body, in which plural layers of copper foil stick to one another with insulating materials interposed there-between, and the laminated body, in which plural layers of copper foil stick to one another with insulating materials interposed therebetween, comprises a laminated body, in which an insulating material mixed with a high dielectric filler as the insulating materials and having a dielectric constant of 10 or more as a whole is used to stick the plural layers of copper foil.
In a further aspect of the invention, preferably, the step of forming a plurality of independent conductive paths, which are provided in regions of the insulating resin layer filled in the windows of the copper foil, and extend from a front side of the substrate to a back side thereof, comprises the steps of (1) providing a plurality of through openings as second windows in regions of the insulating resin layer filled in the windows of the copper foil; (2) applying copper plating on the insulating resin layer, which fills the second windows and covers the copper foil; and (3) selectively applying etching on the copper plating, which is formed on the insulating resin layer, to form lands on at least opening portions of the second windows.
More preferably, the step of forming a plurality of independent conductive paths, which are provided in regions of the insulating resin layer filled in the windows of the copper foil, and extend from a front side of the substrate to a back side thereof, comprises the steps of (1) forming second windows in regions of the insulating resin layer filled in the windows of the copper foil, the windows having a plurality of convex and concave portions, which portions are disposed radially and in which mountains and valleys are cyclically present in the wall surfaces with the mountains and valleys adjacent to each other to be spaced a substantially equal distance from centers of the windows; (2) applying copper plating on the insulating resin layer, which covers inner walls of the second windows and the copper foil; (3) mechanically polishing the inner walls of the second windows to selectively remove the copper plating on the convex portions to leave the copper plating on the concave portions; and (4) selectively applying etching on at least the copper plating around the opening edges of the second windows among the copper plating formed on the insulating resin layer to form lands connected to the copper plating in the concave portions in the second windows.
Further, the step (2) of applying copper plating on the insulating resin layer, which covers inner walls of the second windows and the copper foil, comprises the step of applying a plating catalyst by chemical copper plating on the concave portions of the second windows without applying copper plating on the convex portions, and wherein the step (3) of mechanically polishing the inner walls of the second windows to selectively remove the copper plating on the convex portions to leave the copper plating on the concave portions is dispensed with.
Also, the step of forming second windows in regions of the insulating resin layer filled in the windows of the copper foil, comprises laser beam processing.
The laser beam processing for forming the second windows comprises using triple harmonic waves and quadruple harmonic waves of the YAG laser and performing projection irradiation of an aperture composed of a plurality of independent figures, whereby the processing for formation of a plurality of holes is performed at a time.
A pretreatment for the step of copper plating comprises coarsening surfaces of the insulation resin layer including the side walls of the second windows and subsequently performing chemical copper plating after a plating catalyst is applied.
When a semiconductor chip is mounted on the multi-layer wiring substrate, it is possible to realize a semiconductor device, which is packaged in high density.